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VMETRO's serial FPDP IP core supports Xilinx Virtex-5 FPGAs
Serial FPDP IP core from VMETRO provides high-performance, highly integrated solutions for both front panel optical and VITA-41 (VXS) backplane interconnects.
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By
Clive
Maxfield
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Programmable Logic DesignLine
(09/17/2007 0:09 PM EDT)
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VMETRO has expanded the use of its Serial FPDP IP core to support Xilinx Virtex-5 FPGA-based products utilizing RocketIO GTP multi-gigabit serial transceivers. The combination of VMETRO's hardware and the sFPDP IP core provides high-performance, highly integrated solutions for both front panel optical and VITA-41 (VXS) backplane interconnects. Application areas for this combined Serial FPDP I/O solution include real-time imaging, signal processing, high-speed data recording and test systems.
The Serial FPDP IP core is provided in either obfuscated source for simulation or in full VHDL source. The core has been fully tested with – and can be implemented on any – VMETRO Virtex-5, Virtex-4, or Virtex-II Pro, FPGA-based products that utilize RocketIO GTPs or MGTs. These products include the Phoenix VPF2 VITA-41 (VXS) Digital Signal Processor with Dual Virtex-5 FPGAs and Freescale MPC8641D; the Phoenix VPF1 VITA-41 (VXS) Digital Signal Processor with Dual Virtex-II Pro FPGAs and Dual PowerPC 744X; the Phoenix M6000 Intelligent I/O Controller and PMC-FPGA03/F FPGA-based PMC Processing Modules. Subject to licensing conditions, the core can also be used on non-VMETRO based Virtex-5, Virtex-4 and Virtex-II Pro based FPGA products.
For more information, please visit www.vmetro.com.
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