Altera's Stratix II FPGAs provide complete IP protection solution

As FPGAs advance in density, functionality and performance with each new process generation, designers are increasingly using them to perform critical system functions that were traditionally filled by ASICs or ASSPs. The Stratix II design security solution offers benefits for a number of applications and market environments:

• In areas where IP laws are not well enforced, the Stratix II design security feature enables IP protection, resulting in increased revenue retention.
• The Stratix II design security solution allows different security keys to be programmed into different Stratix II devices, enabling product version control and customization.
• The ability to encrypt configuration files in Stratix II FPGAs ensures royalty income for IP vendors, since they can track exact IP usage.
• The tampering protection of the Stratix II design security solution prevents undesired modification of gaming machines.
• The Stratix II design security solution allows military customers to protect core technology and information, and prevent tampering.
• ASSP vendors can test market and adapt the functionality in their ASSPs via Stratix II FPGAs while protecting their IP.

Securing devices with the AES encryption key
Altera claim that Stratix II and Stratix II GX devices are the industry's first FPGAs to support configuration bitstream encryption using the 128-bit AES coupled with a non-volatile key. Selected by the National Institute of Standards and Technology (NIST) and adopted by the U.S. government to protect sensitive information, AES is the most advanced encryption algorithm available today. A user-defined AES key can be programmed into the 128-bit non-volatile key stored in Stratix II devices. The same key is used by Altera's Quartus II design software to generate an encrypted configuration file stored in an external memory or configuration device. At power up, the memory or configuration device sends the encrypted configuration file to the FPGA and the device then uses the stored key to decrypt the file and configure itself. This Stratix II AES implementation is FIPS 197 certified. A comprehensive design security solution for Stratix II GX will be available in the third quarter of 2006.

Designers can easily implement the design security solution, which includes application notes and various on-board and off-board key programming methods, to suit different manufacturing flows. They can select from an EthernetBlaster cable, JTAG Technologies' (www.jtag.com) in-system programming tools, System General's (www.sg.com.tw) socket programming equipments, in-circuit testers, and key programming services offered by major Altera distributors.

To register for Altera's "How to Protect Your IP Using FPGA Design Security" net seminar, visit www.altera.com/netseminar_st2security. For more information about the Stratix II design security feature, visit www.altera.com/st2-security. For more information on how to use the Stratix II design security feature, contact your local Altera sales representatives.