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In the late 1980s memory devices changed in a flash. Intel and Toshiba spearheaded the development of flash process technology to create a new class of products. Prior to flash-based memory devices, designers used electrically programmable read-only memories (EPROMs) or electrically erasable programmable read-only memory (EEPROMs) for non-volatile storage of digital information; both posed major challenges.
EPROMs offered high-densities and were reliable, but could only be erased by exposing the silicon to strong ultraviolet (UV) light. Early EPROMs were packaged with a transparent glass window on the top for this purpose. The glass window significantly added to the cost of the devices so later versions were built with an opaque top, making these devices non-erasable after programming. Engineers lost flexibility to change or update their designs once the memory devices, then known as one-time programmable (OTP) EPROMs, were programmed. Manufacturers also had to account for fallout from programming failures.
The advent of EEPROMs solved the erase problem. Instead of exposing silicon to strong UV light, EEPROMs are programmed and erased by applying high voltage (12V to 20V) to certain device pins. For low-voltage devices, however, a spike in power consumption during programming and erase potentially causes system vulnerabilities. Similar to EPROMs, EEPROMs also require long write and erase times since devices can only be written-to or erased one byte at a time. EEPROMs also have higher costs since each device cell requires a separate read, write and erase circuit, adding to the overall die size.
Flash-based EEPROMs, introduced in 1988, was an answer for engineers looking for high-density, low-cost memory devices that were easy to program and erase. Flash memory devices can be electrically erased in blocks instead of bytes without the need for irregularly high voltages, considerably reducing erase times. This block-based erase method allows the device to share erase circuits within a block, reducing both die size and costs. Densities for flash memory devices have increased exponentially since their introduction, with vendors offering as much as eight gigabytes of storage capacity.
Flash Memory Programming Challenges
Low-cost standard flash memory devices are commonly used in a wide variety of applications to store configuration, program or memory data. Before flash memory devices can be used in a system, they must be programmed. Using traditional methods, programming may require large amounts of time in the manufacturing process. As storage densities for flash memory devices continue to increase, programming times also increase, further magnifying this challenge. This method provides little flexibility for last-minute design changes or programming updates while the product is in the field, capabilities that are increasingly required to add features or address bugs.
Traditional Options for Programming Flash Memory Devices
There are three options for programming today’s flash memory devices. The first option is to pre-program the device before inserting it onto a printed circuit board (PCB). This approach increases the cost of manufacturing since it requires extra fixtures to program the device. Another limitation is that once pre-programmed and mounted, the device cannot be used for other purposes as the design evolves. This option is also inflexible as it does not allow for last-minute changes, enhancements, or bug fixes that may be necessary after the part is inserted onto the PCB.
The second option is to program the flash memory device after it is installed on the PCB, also known as in-system programming (ISP). One way to accomplish this is to first install a small program into an existing microprocessor on the PCB and then have the microprocessor program the device. The microprocessor accesses the small program either in-system or through the use of in-circuit emulation hardware, adding extra equipment and an additional step to the manufacturing process. In this method the data transfer to the flash memory device is inefficient as the microprocessor must first access the data from a different source, store it in any available RAM, and finally program the device.
The third option is to use ISP with a Joint Test Action Group (JTAG) boundary scan chain to control the pins connected to the flash memory device. This option is often used because many flash memory devices do not support the JTAG interface because of cost and space limitations. In this approach, the flash memory device is connected to a JTAG-compliant device on the PCB which acts as a programming host (See Figure 1). Devices such as an application specific integrated circuit (ASIC) or a programmable logic device (PLD) may be used as the programming host. This inefficient method requires shifting hundreds of bits of data through the entire JTAG boundary scan chain to write just a few bits of data to the flash memory device. Another limitation of this approach, when using a PLD host, is that it requires the host PLD to enter a programming mode. This causes the core of the PLD, and other devices connected to the PLD, to temporarily cease functioning.
1. Programming the Flash Memory Device via the JTAG Boundary Scan Chain
Shorten Programming Times
A Parallel Flash Loader (PFL) solution provides an easy, cost-effective way to program flash memory devices through the JTAG interface. The JTAG test access port (TAP) is found on most PCBs since it only requires a small amount of space (four pins) to access all JTAG-compliant devices on the PCB. The solution uses a complex programmable logic device (CPLD) to bridge the JTAG interface and the flash memory device’s parallel address/data interface. Instead of shifting data through all pins on the CPLD, this solution quickly retrieves data from the JTAG scan chain and generates data that is formatted for the receiving target flash memory device. Unlike the JTAG boundary scan chain method, the PFL brings the data through the logic array of the CPLD as shown in Figure 2.
2. Programming the Flash Memory Device via the PFL Method
The solution significantly reduces flash memory device programming time. Using an example of programming a single vector into a 48-pin common flash interface (CFI) flash device, Table 1 shows the potential time saved when using the PFL solution. This example compares the use of a PFL solution with the traditional method of programming via the JTAG boundary scan chain using a JTAG-compatible PLD or ASIC with approximately 200 pins.
In addition to shorter programming times, the PFL solution can be used to configure proprietary FPGAs on the same PCB, using FPGA configuration data stored in a flash device. The PFL logic determines when to start the configuration process, reads data from the flash memory device, and configures the FPGA accordingly. The PFL also supports a proprietary page mode for FPGA configuration (Figure 3). Each page stores the configuration data for a single chain of FPGAs and up to eight different pages can be stored in a single flash memory device. Using this method, hardware developers avoid using dedicated FPGA configuration devices, reducing component costs, shrinking board size and simplifying board design.
3. Configuring Altera FPGAs from a Flash Memory Device via the PFL Method
This method can also be used with application specific standard products (ASSPs) and ASICs. In this case, PFL can be used to send configuration or initialization data to the Flash memory device for ASSPs and ASICs, as with the FPGA scenario. The remaining logic in the CPLD can then be used to implement functions to execute configuration signals to these devices.
Ease-of-Use and Low Cost
The PFL can be easily integrated into a CPLD using a simple GUI within the development software. The GUI enables the user to set the clock frequency, flash memory type, byte address of the option bits and desired supplemental files. The software automatically generates the needed logic for implementation in the device.
The PFL, along with proprietary CPLDs, offers several key benefits over existing flash memory programming options. This implementation takes advantage of real-time ISP, allowing for last-minute design changes, enhancements or bug fixes without sacrificing time-to-market. A new or updated programming file can be loaded at any time during the manufacturing process through the JTAG interface. The PFL solution offers the flexibility to easily make updates in the field without powering down the entire system. Another major advantage of using a programmable logic implementation is design reuse. As data requirements and flash memory devices continue to progress, the PFL solution can still be used with little or no redesign effort required. Therefore, the PFL can easily be ported into new designs or the same design for different platforms.
The PFL method does not require special programming fixtures since the proprietary CPLD uses the JTAG scan chain connections that are already present on the PCB. This results in a reduction in both manufacturing costs and time. Since the PFL only uses a small portion of logic in the CPLD, the remaining logic can be used for other applications such as I/O expansion, system configuration or power-up sequencing. Finally, the PFL function can fit into the smallest CPLD, resulting in a very low component cost.
Conclusion
Flash memory devices offer great value to engineers who seek high-density, low-cost memory devices that are easy to program and erase. Low-cost standard flash memory devices are widely used in a variety of applications to store configuration, program or memory data. Of the three main options used for programming today’s flash memory devices, using ISP with a JTAG boundary scan chain is often the method of choice.
However, this approach has limitations, including requiring considerable data shifting through the entire JTAG boundary scan chain to write just a few bits of data to the flash memory device. Using a PFL solution provides engineers an easy, cost-effective way to program flash memory devices through the JTAG interface. A PFL solution offers many benefits, including shorter flash memory device programming times, streamlining of the FPGA configuration process, ease of use, and low adoption cost.
About the Author
Theresa Vu joined Altera Corp. in 2004 and is currently a senior product marketing engineer. Ms. Vu has spent the last six years in the programmable logic industry. She earned her Bachelors Degree from the University of California, Davis, in 1999. She can be reached at THVU@alterea.com
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