San Jose, Calif. — Beneath the reassuringly smooth surface at the annual TSMC Technology Symposium here last week, the roiling undercurrents of change ran deep and fast.
Change is coming to the business model that has made Taiwan Semiconductor Manufacturing Co. Ltd. a powerhouse. It is coming to process migration, as the giant foundry stares into the depths of 65 nanometers and beyond. And it is coming to the relationship between TSMC and its customers' engineers — change so profound as to alter the meaning of "foundry."
TSMC seems caught in a perfect storm of external forces. Projected slow growth in the overall semiconductor industry is squeezing the total available market for foundry services. Rapidly escalating design costs and the absence of any obvious next big thing are limiting the number of designs likely to migrate beyond the 130-nm process node. And growing competition from across the Taiwan Strait is putting pressure on margins in the mature processes where the bulk of designs appear to be staying.
During the 1980s, the overall semiconductor industry grew at an average rate of 15 percent a year, said F.C. Tseng, deputy chief executive at TSMC. Now the industry is projected to grow only 10 percent a year through 2010.
In total, the foundry business hit $16.3 billion in sales in 2004, according to TSMC. In the pure-play arena, TSMC was the market share leader, with 46 percent of the business, according to research firm IC Insights. United Microelectronics Corp. claimed 23 percent, while Chartered Semiconductor held 7 percent and Semiconductor Manufacturing International Corp. (SMIC) had 6 percent. Other foundries accounted for the rest.
The foundry business is expected to slow this year. Len Jelinek, principal analyst at iSuppli Corp. (El Segundo, Calif.), projects that the overall IC industry will grow faster than the pure-play foundry business, partly because of the current down cycle. In 2005, iSuppli projects, the overall IC industry will grow 6 percent over 2004.
Disappearing designs
As the industry decelerates, new killer apps are elusive. The design wins that fabless companies are finding are often narrow, highly specific and short-lived, according to industry executives — exactly the wrong profile for a new process with a long development cycle and very large numbers of dice per 300-mm wafer.
Meanwhile, the cost for a new design is tripling with each succeeding process node, said Shang-Yi Chiang, senior vice president of R&D at TSMC.
"Where it cost around $30 million to design an entirely new chip at 90 nm, that cost will approach $100 million for a 65-nm design," he said. "Only very high-volume, standard-product ICs, such those for programmable logic, cellular handsets and graphics, can justify the design cost."
This is leading not only to fewer design starts but also to fewer fabless companies. "There are higher barriers to entry now," said Kenneth Kin, TSMC's senior vice president of worldwide sales and service. "We are seeing more consolidation and fewer startups in the fabless area. And the size of surviving fabless companies is growing. The best of them now are as large as the tier-2 IDMs [integrated device manufacturers]."
In the past, the strategy that has kept foundries healthy during the transition to a new, high-margin process node has been their ability to maintain solid margins on more-mature processes, where the bulk of wafers are run. But this will prove increasingly difficult for TSMC as the power of mainland Chinese foundries such as SMIC and Grace continues to grow. These foundries are already producing excellent results at 130 nm, and by slashing prices on 180-nm wafers to reportedly below $1,000, they have actually caused some design teams to migrate their designs back a generation instead of forward.
"We have customers now who have to take their tapeouts to someone like SMIC," said Naveed Sherwani, president and CEO of design house OpenSilicon. "If your chip is out there competing against one from Samsung, you can't afford to be getting your wafers from TSMC."
In this environment, TSMC must specialize to maintain margins even at 130 nm. "We will rely on specialty processes to increase margins from our mature fabs," said Kin. These specialty modules will include mixed-signal, nonvolatile memory and other delicate process additions that can attract high-margin business from certain design teams.
Meanwhile, except in some very specific cases where the overall performance of a chip is determined by the feed of a few critical delay paths, designs are seeing little or no performance gain at 90 nm over a fast 130-nm process, sources report. Such gains are possible on paper, but by the time the design has been brought into compliance with design-for-manufacturing guidelines, optimized to bring power consumption within tolerable levels and imbued with sufficiently large guardbands accommodate process variations, the advantages have vanished. The motivation of increased circuit performance that has driven process migration since the beginning of CMOS has essentially ended.
Instead, design teams with entirely different motivations are leading the trickle of migration to 90 nm and beyond, to 65 nm. One motivation is the pursuit of increased system-level performance, not through faster circuits but by higher integration. This appears to be the case in a number of areas but particularly in high-end processors and graphics chips.
In both those situations, much higher transistor density makes it possible to put more CPU cores, more graphics pipelines and — particularly — more local memory on the die. By increasing the amount of parallelism on the die, instantaneous processing rates go up. More important, by eliminating more chip-crossing latencies and DRAM latencies during memory accesses, architects remove one of the dominant glitches in system performance.
This has led to increased interest in huge, fast, on-chip memory structures. That fact is reflected by TSMC's schedule change for one-transistor SRAM. "Starting in about May last year, we began to see surprising customer interest in our 1T SRAM technology at both 90 and 65 nm," reported Chiang. "This has led us to pull in the schedule for this module. Now we are trying to release the 1T SRAM module for 65 nm at the same time as the logic process."
Powerful motive
Another key motivation is power. Even though leakage currents are a huge issue with fast transistors at fine geometries, it is possible — using a combination of low-leakage transistors, voltage islands and aggressive dynamic voltage-frequency scaling — to slash system power by moving to 90 nm, and again by moving to 65 nm. This is a primary motivator for the FPGA industry, around whose neck power consumption is a persistent albatross, and for the cellular handset industry, which sees power as a metric for feature sets and battery life.
"The cellular baseband developers are the first ones to move to the next technology node," Kin said. "We are responding to market needs. It's not that we're deemphasizing speed, we're just shifting our priorities. We are going to use low power as a technology driver."
Accordingly, when TSMC moves its 65-nm process into risk production this fall, it will be the low-power variant that becomes available first. The high-performance version won't come up until early in the third quarter of 2006, under the present schedule, and the general-purpose variant will follow later in that quarter.
As if these challenges were not enough, TSMC has warned its customers that success at 90 and, especially, at 65 nm will require a whole different kind of relationship between design team and foundry.
First, the concept of design rules will join the walking wounded. "There will be a tendency to move toward more and more guideline rules as we go to 65 nm," Chiang said. "We are in the process of formulating the rules now, so I can't even estimate how many there will be. I think the current design-rule-based model will still work at 65 nm, but only with much greater cooperation. The things that are happening in the process now are almost impossible to capture in a design rules manual."
In general, he said, "process variations in such things as critical dimensions are becoming more and more difficult to control as process geometries shrink. To some degree, we can control the variations with automatic process controls. For instance, we use a combination of feed-back and feed-forward controls to control poly line width. We feed forward measured poly thickness to adjust our etch time. And we feed back measured line width data to control mask exposure."
But that strategy becomes "very difficult" for some parameters, Chiang said. Chemical mechanical planarization is a good example. "The variations in metal thickness are dependent on the density of metal lines in the area, so what we have to do is ask the design team to participate in feed-forward control. They have to control their metal line density by inserting additional lines, so that the CMP process can produce more-uniform results. That screws up the timing of the design, so the design team has to use better extraction tools."
In the end, Chiang said, the only solution is close cooperation between design engineers and foundry engineers. "We need to get this message across. Design will not be effective at 65 nm without a close partnership."
And this partnership will have to be multidisciplinary. As an example, Chiang offered the data that TSMC is now collecting on strained silicon, which will play a key role in the 65-nm process. "We are learning more about the variations that come with strained silicon," he said. "Many things affect the degree of strain, including the configuration of metal above the transistor, at all layers; the degree of back-grinding the customer applies to thin the wafer; and the stresses imposed by the package. In addition, strain on each axis has a different impact on mobility." Thus, "We have to have very good 3-D mechanical modeling of the finished die in the package just to understand the mobility in the channel of an individual transistor."
These challenges, Chiang emphasized, will have to be shared with the design team. "I think it will be very difficult for a fabless company to be successful at these nodes without internal process expertise," he warned. As process control loops extend clear back into the physical-design process, it will be necessary for design teams to run technology-CAD models provided by their foundry partner.
Sensitive information will be flowing in both directions, so the relationships will have to be intimate, Chiang speculated.
