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Highest-density LatticeECP3 in volume production





Programmable Logic DesignLine

SAN FRANCISCO—Lattice Semiconductor Corp. announced that its LatticeECP3-150 mid-range FPGA has been fully qualified and released to volume production.

The LatticeECP3-150, the highest density FPGA in Lattice's mid-range, low-power ECP family, features a DSP capacity of 320 18x18 multipliers, 6.8 Mbits of memory and up to 16 3.2Gbps serdes channels, making it suited for complex and integrated wireless remote radio heads (RRH) such as MIMO-based RF antenna solutions, according to Lattice (Hillsboro, Ore.).

The ECP3-150 also provides wireline access developers with high-density, low-cost, low-power Ethernet, SONET and PCI Express solutions, the company said.

Lattice and its third-party partners offer a range of intellectual property (IP) cores for the ECP3-150, the company said. These include crest factor reduction , digital pre-distortion, CPRI, OBSAI, Serial RapidIO, XAUI, SGMII/Gigabit Ethernet, PCI Express, SMPTE for serial connectivity, FIR filters, FFT, Reed-Solomon encoders/decoders, CORDIC, CIC, NCO for DSP functions and several others for memory interfaces and connectivity, Lattice said.

The LatticeECP3 FPGA family is supported by the ispLEVER design tool suite, version 8.0, Lattice said.

LatticeECP3-150 devices are available now in two low-cost wirebond packages (672 fpBGA and 1156 fpBGA), Lattice said. Prices for the LatticeECP3-150 in the 672 fpBGA package in 25,000- unit volumes start at $75, according to Lattice. The LatticeECP3-70 and LatticeECP3-95, which were production released in February, are priced at $35 and $50, respectively, in 25,000-unit volumes, the company said.

 
Related Links:
  • Lattice FPGA design suite adds support for DDR interfaces
  • Lattice rolls 65-nm FPGAs and programmable clock chips
  • Lattice Semiconductor's third generation FPGAs consume half the power of competitive devices






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