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The folks at Lattice Semiconductor have announced the immediate availability of their ispLEVER 7.1 FPGA design tool suite. This latest release delivers a number of new functional and performance-enhancing features, including the industry's first dedicated FPGA Simultaneous Switching Output (SSO) Analyzer.
The SSO Analyzer enables FPGA designers to actively analyze and optimize I/O pin placement and output switching characteristics to minimize undesirable noise and ground bounce on a printed circuit board. To enable designers to achieve higher levels of productivity, the ispLEVER 7.1 design tools also deliver up to 30% faster FPGA design compile times and now support multi-processor powered design compilation to achieve the fastest timing closure.
An enhanced Power Calculator enables FPGA designers to analyze and optimize power requirements early in their design. The Lattice Power Calculator is said to include an exceptionally user-friendly interface that enables power analysis at the block level and examination of "what-if" scenarios by changing design environment variables.
This release also marks the addition of Synplicity's Synplify Pro and Aldec's Active-HDL Lattice Edition as principal elements of the ispLEVER FPGA design flow. Mentor Graphics' Precision RTL synthesis and ModelSim simulator continue to be supported as standalone tools for Lattice FPGA design and are available directly from Mentor Graphics. Both Lattice and Mentor Graphics remain fully committed to support Lattice's existing and future programmable devices with Mentor Graphics tools.
New features
The ispLEVER 7.1 release includes enhancements and new features in virtually every aspect of the design flow. A partial list of new features and enhancements includes the following:
- Windows Vista O/S Support
- "Find Module" Function in Project Navigator
- Interactive Synthesis Flow
- Design Planner Enhancements
- SSO Analyzer
- Interactive Trace Report
- Find and String Filters
- Enhanced EBR and DSP Block Information
- Color Coded Port Groups and DQS Span
- Improved Pin Display Select Dialog
- Preprocessor Directives for Design Preference Files
- Map Place and Route (MPAR) Enhancements
- Multi-core Processor Support for Batch Runs of Place and Route
- Congestion Driven Routing Options
- Guided MPAR
- Reveal Logic Debugger Tool – Expanded VHDL Support
- Boolean / Integer
- Enumerated Data Types
- Power Calculator Enhancements
- Effective Thermal Resistance
- Power Graph
Higher performance
The ispLEVER 7.1 release marks a new standard in performance, encompassing improvements in post-route design operating frequency of up to 5% and runtime reductions by as much as 30% for larger designs. These improvements decrease costs, speed-timing closure, and help users deliver the best solutions more quickly.
LatticeMico32 embedded microprocessor release
A recent release of the LatticeMico32 embedded processor solution included Linux O/S-based tools, VHDL language support (through VHDL wrappers of the Verilog IP), and added arbitration support.
The new ispLEVER 7.1 release seamlessly integrates the LatticeMico32 Mico System Builder into its design flow. The new arbitration support automatically selects the appropriate Wishbone Bus arbitration scheme when the microprocessor platform is generated, enabling shared-bus or slave-side arbitration. This capability allows multiple master ports efficient access to multiple slave ports.
Lattice also has recently added the uClinux O/S to a portfolio that already included RTOS support from Micrium and µITRON. The release of ispLEVER version 7.1 is the first that includes the latest LatticeMico32 support.
About the Lattice ispLEVER Design Tool Suite
The ispLEVER design tool suite is Lattice's flagship FPGA design environment for use with its latest FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, timing analysis, place and route, in-system logic analysis and more. The ispLEVER tool suite is provided on CD-ROM and DVD for Windows Vista, UNIX and Linux platforms.
About Aldec's Active-HDL Lattice Edition
The new OEM agreement between Aldec and Lattice enables Lattice to bundle the Active-HDL Lattice Edition with its ispLEVER suite, and Active-HDL Lattice Web Edition with Lattice's ispLEVER Starter and ispLEVER Classic design tool suites.
Active-HDL Lattice Edition features mixed language simulation of VHDL and Verilog, co-simulation with The MathWorks Simulink, and many advanced verification and debug features such as Language Assistant, Code Execution Tracing, Advanced Breakpoint Management and Memory Viewing.
About Synplicity's Synplify Pro
Synplify Pro will now be bundled with the ispLEVER design tool suite and will deliver a number of advanced synthesis features to Lattice FPGA designers, including mixed VHDL and Verilog synthesis, automatic register balancing and HDL-Analyst.
Standard Synplify will continue to be available for use with Lattice ispLEVER Starter and ispLEVER Classic design tools.
Pricing and availability
Lattice's ispLEVER 7.1 for Windows, Linux and UNIX users is available immediately without charge for customers with active design tool maintenance. The full ispLEVER design tool suite starts at a price of $895 for the Windows version.
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