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Mezzanine card design makes FPGA integration easy
VMETRO announced its first FPGA Mezzanine Card (FMC/VITA 57) module dubbed the ADC510, which is available in air-cooled and conduction-cooled rugged versions.
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By
Ismini
Scouras
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Courtesy of
eeProductCenter
(04/29/2008 9:18 AM EDT)
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Houston, Tex.VMETRO announced its first FPGA Mezzanine Card (FMC/VITA 57) module dubbed the ADC510, which is available in air-cooled and conduction-cooled rugged versions, integrates two 12-bit 500MHz A/D chips for use in DSP applications such as Signal Intelligence (SIGINT), Electronic Counter Measures (ECM), and Radar.
This design, based on the emerging VITA 57.1 standard, makes it easier for developers to integrate FPGAs into their embedded system designs. The ADC510 supports two Texas Instruments ADS5463 A/D converters with each device supporting a sampling rate up to 500 MSPS and providing 12-bits of digital output. The A/D converter interfaces are routed to the FMC connector to enable an FPGA on a baseboard to directly control and receive data.
There is a choice of sample clock sources for the ADC510, including an onboard source that supports sampling rates of 300, 320, 400, and 500 MSPS as well as the ability to utilize an external sample clock. Input and output triggers are provided to enable multiple ADC510 modules to be synchronized to increase the number of input channels.
FMCs address the needs of FPGA centric I/O by enabling I/O devices that reside on an industry standard mezzanine card to be attached to, and directly controlled by, FPGAs that reside on a baseboard. The benefits of FMCs are a small footprint, reduced I/O bottlenecks, increased flexibility, and reduced cost by removing redundant interfaces. An FMC module is about half the size of a PMC mezzanine module. To maximize data throughput and minimize latency, the FMC connector has many pins that support high-speed signals for moving data between the FMC and an FPGA on the baseboard. FMCs are ideal for high speed analog I/O, digital I/O, fiber-optics, memory or even a DSP co-processor.
VMETRO makes available HDL example code for the ADC510 for integration into the HDL development suite for VMETRO FPGA baseboards.
Pricing: $8500.
Availability: Now.
Datasheet: Click here.
VMETRO, www.vmetro.com
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