|
The folks at Ambric are known for their highly-scalable massively parallel processor array (MPPA) devices. An MPAA boasts hundreds of processor cores on a single chip that delivers TeraOPS-class performance.
Creating applications that take full advantage of multiple cores has always been challenging. The problem is only exacerbated when one is dealing with devices containing hundreds of heterogeneous cores. Previous solutions typically required users to employ separate tools and disparate methodologies to program each type of core. These solutions also left the user responsible to "tie everything together and make it all work."
The folks at Ambric say that they came at things from a completely different angle. They started by considering the programming model, and they then developed the software tools and hardware architecture that met this model.
Introducing aDesigner
The solution on the hardware side of the fence was the MPAA. The solution on the software side of the fence was aDesigner, a comprehensive, easy-to-use tool suite that uses Ambric's structured object programming model (SOPM) to make software development practical for embedded application developers facing the challenges of programming massively parallel processor-based systems.
With aDesigner, it is possible to program hundreds of processors on a single chip. Prior to this, programming tools only provided the capability to program a handful of cores.
Furthermore, synchronizing communication among cores or processors was left up to the individual programmer's ingenuity. This is a daunting task that includes debugging, testing, and optimizing the inter-processor communication and shared memory between cores or processors so as to meet chip-level timing constraints.
The aDesigner suite addresses this by offering a single integrated development environment (IDE) for seamless programming across hundreds of processors, leveraging channel communication built into the Am2000 MPPA and enabling users to synchronize debugging across all processors. This greatly reduces program development time, thereby accelerating time-to-market.
New performance analysis capabilities
Programming a multi-core device is only part of the problem. Once an application is running, it is necessary to have some way of implementing performance analysis to see which processor cores are running "hot" (at the limit of their capabilities) and which are running "cold" (which means they are being under-utilized).
Thus, the latest release of aDesigner provides added performance analysis capabilities that facilitate the optimization of program execution across hundreds of processors. The new aDesigner enables a significant productivity boost by allowing users to optimize and tune their designs during both simulation and real-time hardware execution.
Graphical debugging within aDesigner.
(Click this image to view a larger, more detailed version)
color coded status of all processors at the bottom. There is a slider to determine window size (how many processors you want to view) and ability to zoom in and out. On the top, one can zoom into activity within a single processor shown in this picture.
Of particular interest is that fact that users can view processor and channel bandwidth utilization in hardware without impacting or in any way perturbing the real-time performance of the design.
This is a very powerful and useful capability for optimizing, debugging, and performance-tuning the design. aDesigner gives users the ability to view the design at all levels – chip, multi-processor, and individual processor – by using the on-chip dedicated debug network built around every Am2000 T MPPA. Also, users can identify hot and cold spots within the design – processors with high and low utilization – which facilitates design load balance. This capability can significantly improve overall throughput.
Color coded status of all processors is shown at the bottom of this window. There is a slider to determine the window size (how many processors you want to view) and the ability to zoom in and out. On the top, one can zoom in to see the activity within a single processor, if required.
(Click this image to view a larger, more detailed version)
In addition, users can target code inside a single processor, tweak the code to increase the performance of that processor, and then assess the impact of that change across the group of interconnected processors, as well as across the entire Am2000 MPPA device. And users have the ability to measure and analyze activity between any two events across hundreds of processors so as to improve latency. Users can also identify and address data bursts within streaming data so that design performance can be readily improved.
Multicore EXPO, NAB, and ESC
Ambric will be demonstrating aDesigner at Multicore EXPO in Santa Clara, April 1-2 in booth 23, at NAB in Las Vegas, April 14-17 in booth SU13213, and at ESC in San Jose, April 15 -17 in booth 1910.
About aDesigner
The aDesigner tool suite's powerful graphical user interface (GUI) serves as a cockpit for the user to program the Am2000 MPPA. The design creation, simulation, compilation, realization, and debugging tools – which are included in the tool suite – enable easy creation, verification, and real time execution of the objects that collectively form the complete design.
The aDesigner IDE uses the widely-deployed Eclipse framework, a mature and familiar platform, to accelerate developers' migration. The built-in simulator provides cycle-accurate behavior of the design, and the compiler has a unique optimization capability that takes into account user-defined constraints at both local and global levels. The realization tool enables mapping of the design on single or multiple devices. And the debugger enables bugs to be detected during design simulation and design execution in the real-time hardware system. Together all these tools work seamlessly within aDesigner.
A deterministic and practical approach to system design and programming is possible through the Ambric structured object programming model (SOPM), a patented technology that the Am2000 family architecture was built around. The Am2000 architecture was created by first considering the needs of developers in a MPPA environment and then creating a hardware architecture to support those needs. This has resulted in a tight coupling of the programming model and the silicon architecture so that customers can develop applications in weeks, as compared to months with conventional tools.
aDesigner also slashes development time because hierarchical objects can be created and then reused to easily build complex objects in software and on the Am2000 MPPA. These objects can be encapsulated and replicated on the same MPPA, as well as across multiple MPPAs. Executing these objects then becomes a simple task as each object is self-contained and control free so there is no global timing closure issue to deal with.
Availability and pricing
The new aDesigner software development tool suite is available today. List price starts at $1,495.00 U.S. For more information about aDesigner, contact Ambric at sales@ambric.com.
|
