Convert an FPGA to a gate array at project start

A successful semiconductor product often goes through a field-programmable gate array (FPGA)-to-gate array conversion as an afterthought. But what happens if this step is taken with forethought? Considering the gate array option early in the design process can increase a product's chances of success.

Selecting a gate array early in the design cycle can bring with it many advantages. For example, a design that draws less power may also have less demanding cooling requirements, a less expensive power supply or a smaller battery. Likewise, a designer can realize a smaller footprint by foregoing pin compatibility, selecting a smaller package and even consolidating multiple chips onto one gate array.

Bringing multiple specification advantages to a product offers rich rewards, but sometimes a single advantage alone makes it all worthwhile. Low standby power by itself may make or break a battery-powered product. Reducing electromagnetic interference (EMI) because of the availability of a spread-spectrum clock generator (SSCG) and embedded capacitors can save time and money and make it easier for a product to pass Federal Communications Commission (FCC) compliance testing. Increasing logic speed by four or five times for the same technology and increasing total logic density may allow more internal parallelism. Eliminating most soft errors stems the tide of seemingly random customer problems that surface daily among the company's products.

Gate arrays can have gate counts ranging from more than a thousand down to only one. Converting a completed FPGA design to a gate array can take three months, three weeks or less than three days, depending on the complexity of the conversion. Three-month conversions represent the high end in performance and complexity, even for the largest conversions. Three weeks is a good rule of thumb for larger designs that have relatively straightforward synchronous conversions. An experienced team whose small designs (10,000 ASIC gates or 100,000 "system gates") are planned from the outset for conversion can complete conversion in only a few days.

A gate array is commonly described as a "sea of gates" prediffused on a die that is customized into two to six layers. However, "sea of gates" is a misnomer. The architecture is actually a sea of n- and p-channel transistor pairs that allow highly efficient implementations not only of gates but also of SRAM and flip-flops. By customizing the metal instead of the many base layers forming the transistor structures, designers can avoid the high NRE costs characteristic of full cell-based designs while improving turnaround times, because the base wafers are readily available in stock.

Conversions can be completed using in-house ASIC designers or subcontracted design houses. As a subset of the ASIC category, gate arrays will look familiar to those with in-house expertise. Popular design tools include the Synopsys Design Compiler tool, used to synthesize register transfer level (RTL) code into a simulated netlist, and the Synopsys Primetime static timing analysis solution, used for back annotation. Gate array suppliers typically supply design libraries at no additional charge.

Some customers choose to subcontract the work in order to avoid purchasing the necessary design tools. The FPGA's RTL source code supplies the raw material for the conversion process, which is performed by a design services house or by the gate array supplier. Customers without an ASIC engineering resource typically favor the "turnkey" design services approach, turning to gate array suppliers, who either provide design services or bring in third-party partners to do the job.

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The cost of conversion includes design services and mask charges. Most design houses will quote design services by the job, not by the hour. Nevertheless, the size of the job ultimately boils down to manpower hours. Fees typically cover wages, equipment, software licenses and other overhead. Spurred on by the potential for repeated customer business, the design services industry has become highly competitive and cost-effective, averaging about $6,000 per person per week.

Total non-recurring engineering (NRE) costs vary by process technology. At NEC Electronics, for example, costs start at $10,000 and $20,000 for the company's two mainstream CMOS-N5 and CMOS-9HD gate array families (which account for almost half of all designs) and increase to $40,000 and $70,000 for the three families used in designs whose performance and density are the most demanding. And at the low end of the spectrum of NRE expenses are higher I/O voltages, up to 5V! Clearly the NRE costs for gate arrays are extremely low in comparison to costs for cell-based ASICs that require customization of all wafer layers. NRE costs are also low in terms of the overall investment a company must make, throughout many generations of product design, to achieve the "special sauce" that outperforms competitors' products.

Technical hurdles of conversion
Depending on the particular conversion, some FPGA features may or may not be appropriate for a gate array. The power-on reset (POR) function is a case in point. In a gate array, a RESET input must be used instead. High-speed serial I/Os are not supported in gate arrays, but parallel I/Os can be used instead. In general, it is best to avoid the use of FPGA-specific intellectual property (IP), rather preferring customer IP and synthesizable third-party IP.

It is also very important to fully document an FPGA's design. Although it is possible to tweak the synthesis or FPGA layout for, say, fine-tuning of delays and yet not reflect the change in the source RTL or design constraints, designers should avoid this, because the RTL (not the synthesis or layout) is what is converted to a gate array. Constraints are optional in FPGA designs, but they are required in gate arrays. Fortunately, they are becoming a normal part of FPGA designs today, which means that no extra effort is required for gate array conversion.

The technical risk of conversion is very low except in unusual cases, such as ones in which a design is asynchronous, depending on precise timing of delay lines. Gate array suppliers will help identify such exceptions after examining a design.

Many customers make use of the high logic performance and density advantages that gate arrays offer, but pushing these benefits too far can impact schedules. Although the customer and the design services house handle the front-end design, the gate array supplier is responsible for the back-end design, which consists of final placement and routing as well as back annotation of timing. Both teams are affected when timing closure becomes more difficult and time-consuming. For this reason, the gate array supplier evaluates feasibility early in the process to ensure that appropriate technology, whether gate array or cell-based ASIC, is selected.

Pin compatibility is another compelling reason to consider gate array conversion early in the design stage. It can be disappointing to finish an FPGA design only to learn that there are no pin-compatible gate arrays available, or that a more economical FPGA-to-gate array pairing could have been made.

Chris Tennant is Program Manager for the Custom SoC Solutions Strategic Business Unit at NEC Electronics America, Inc. He holds a bachelor's degree in electrical engineering (BSEE) from the University of Illinois at Urbana-Champaign.

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