High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems

Television and cinema have entered the digital age. Video pictures are used to transport at standard definition rate (270 Mb/s), upgraded to high definition rate (1.485 Gb/s), and are now migrating to 3 Gb/s. The migration to higher speeds enables higher resolution images for entertainment, but it also presents challenges to hardware engineers and physical layout designers. Many video systems are implemented with feature-rich FPGA and multi-rate SDI integrated circuits that support high performance professional video transport over long distances. FPGAs demand high density routing with fine trace width while high-speed analog SDI routing demands impedance matching and signal fidelity. This paper outlines the layout challenges facing hardware engineers and provides recommendations for dealing with these challenges.

FPGA/SDI Sub-Systems
In a typical FPGA/SDI board, digital video signals are routed between BNC connectors and high-performance SDI analog integrated circuits with 75Ω traces. The interconnection between the FPGA and the SDI integrated circuits consists of several pairs of 100Ω differential signals routed through the fine pitch ball grid of the FPGA. One of the layout challenges is the co-existence of the 75Ω single-ended trace and the 100Ω differential traces. Very often, both types of traces are routed on the top layer where the components reside. Trace widths good for 75Ω may be too wide for running 100Ω traces. Figure 1 is a simplified block diagram of a FPGA/SDI board showing the 75Ω and the 100Ω domains.

Figure 1. Typical FPGA/SDI Block Diagram (click on image to enlarge).

Page 2: SDI Layout Challenge
Page 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 Related Links: Altera announces Cyclone IV FPGAs Lattice, Epson Toyocom offer differential reference clock solution National Semiconductor introduces industry's first 3G-SDI dual SerDes Xilinx unveils platform for broadcast connectivity New triple-rate SDI reference designs from Xilinx

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