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Many IC designers wake up at night with nightmares involving mixed-signal design. A classic example involves the design of high speed serializers and deserializers (SerDes). If a process is selected which will allow good performance on the analog sections of the design – for example phase locked loops, cable drivers, and very high speed sections – then there is invariably a compromise in cost and power when it comes to the digital section.
Meanwhile, if a process is selected with an eye to low cost and low power dissipation, then the resulting small transistors struggle to meet analog requirements. If IC designers don't do a good job of their task, then the nightmares are passed on to the equipment and system designers.
One way to avoid these nightmares is to partition the task in such a way that the bulk of the analog tasks are housed on one chip manufactured in a process optimized for analog performance. Digital functions, meanwhile, should be placed on a different piece of silicon. This is the concept behind National Semiconductor's FPGA Attach video SerDes products.
The specific SerDes parts to be designed were intended for use by the broadcast video industry. Broadcast video has very specific ways of formatting and scrambling the data prior to serialization and transmission. Although there are a limited number of data rates in common use (270 Mbps, 1.485 Gbps, and 2.97 Gbps), there is a plethora of different video formats, each with slightly different formatting requirements. To make matters worse, whenever an ASIC designer releases a chip believed to support all the formats, new formats are then added to the list.
When National's design team looked at this application, the decision was made to design a chip with all of the analog portions required to implement the physical layer (PHY), along with an interface specifically designed to work with low cost FPGAs, and then to generate IP (intellectual property) which would implement all of the digital functionality in programmable logic. When new formats were devised, they could be easily accommodated with an edit to the FPGA code. The resulting products were the LMH0340 serializer, the LMH0341 deserializer and a suite of IP.
Interchip interface
The engineers who developed the Serial Digital Interface standards (SMPTE 259M, SMPTE 292M and SMPTE 424M) must have spent many sleepless nights working on how to generate system problems with the serial standard. To begin with, they targeted the poor unsuspecting EMI engineer by defining the standard around a coax cable, which usually is a good way to limit EMI. Then they defined the parallel side to be either 10- or 20-bit wide words, with coding implemented in a format guaranteed to provide many transitions from 0000000000 to 1111111111 at a set frequency.
One of the best ways to generate EMI is to take a wide CMOS bus and have it switch back and forth between all '0's and all '1's. The SMPTE standards indicate the start and end of each video line with a special character, known as a TRS – or timing reference signal. This TRS includes a transition from 0000000000 to 1111111111 in it.
Inside the serializer this data is scrambled prior to serialization. That way the serial side of the interface does not incur a big disruption, and there is not much of an EMI problem. But for a traditional serializer, sending the TRS over the parallel bus to the serializer is an invitation to EMI.
When defining the interface between the two halves of the serializer, the designers decided to bury this 10-or 20-bit wide bus within the FPGA to make the interface between the two a 5-bit wide bus. The 5-bit bus was also made differential, and the data is transferred from FPGA to PHY after having been scrambled. If you're an EMI engineer, you may now go back to sleep and not worry about broadcast video EMI issues – those nasty engineers who wrote the SMPTE standards can't bother you any more.
Jitter
Jitter plays a prominent role in the nightmares of SDI interface designers. For the serializer, there is a requirement that the output jitter not exceed 0.3 unit intervals (UI), and should ideally be kept at less than 0.2 UI. On the receive side there is a SMPTE specification which requires that jitter tolerance exceed 0.5 UI. Processes that can efficiently implement high speed digital logic tend not to do so well when they are asked to process low jitter, high speed signals.
During National's own tests – based on passing the spectrum of a clock signal through the DCM of an FPGA – it was shown that at 3 MHz, 25 dB of jitter is added to the FPGA output clock signal. Unless the serializer is able to reject some of this jitter, there will be no hope of meeting the output jitter specifications.
Fig 1 shows the jitter transfer function of the LMH0340 serializer, and you can see that at 1 MHz, any jitter that is received by the device is rejected prior to serialization. This means that the system designer just needs to worry about low frequency jitter. The result is an output jitter of 30 ps, which is well below the 0.2 UI (65 ps) suggested target.
1. Jitter transfer function of the LMH0340 serializer.
The eye diagram of the LMH0340 serial output can be seen in Fig 2. On the receive side, the same technology is used on the deserializer to allow for jitter tolerance which again, exceeds SMPTE specs with margin.
2. Eye diagram of LMH0340 serial output.
(Click this image to view a larger, more detailed version)
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