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FPGAs are a valuable technology for designing and prototyping digital logic into medium-volume, medium-density applications. Their high unit cost, however, makes an FPGA cost-prohibitive to move into production. Several alternatives exist for taking a digital design implemented with an FPGA into production, including Structured ASICs, cell-based ICs, and gate arrays, all of which offer lower cost, higher performance, lower power consumption, and time-to-market advantages. While the thought of migrating an FPGA design into an ASIC can be overwhelming to a design team, teaming with an experienced ASIC vendor can help ease the process.
Designing a new product in an FPGA allows for design modifications to be made quickly in hardware. Once the design code is stable and the product is ready for production, a migration from an FPGA to a mid range ASIC can cut the production unit cost by one tenth. The low non-recurring engineering (NRE) charges associated with a mid-range ASIC solution coupled with a much lower unit cost make this strategy a powerful tool in achieving low overall costs, giving users a competitive cost advantage in the market.
To help ease the migration process, several items must be considered during the initial design flow. Designs are becoming larger and more complex and the use of specialized IP is now commonplace. Careful selection of IP early during the design phase is essential. In addition, developing the FPGA and ASIC in a parallel design flow will help to speed the process. Finally, planning for portability to an ASIC from the beginning of the project will help to speed time-to-market and decrease costs (Fig 1).
1. Conversion checklist.
Good design practices such as the use of synchronous design techniques will enable the design to be ported across many different technology platforms. And finally, one of the most important things a design team can do is have good documentation of the design. If a little time and effort is used in the early stages of the design, the migration will require minimal engineering resources. The migration can result in a drop in replacement part or, for additional cost reduction; it can be ported to less expensive technology nodes and/or packaging.
Intellectual property (IP)
When designing in an FPGA it is important to understand long-term IP needs. Many FPGA vendors make small modifications to standard IP due to their architecture, and licensing agreements may prevent the designer from moving any FPGA vendor specific IP to an ASIC. If a program is intended to go into volume production, third party or ASIC vendor IP should be used and agreements negotiated so that the IP can be used in both the FPGA and ASIC implementations. The idea is to make the design as technology-independent as possible. This will allow for an easy migration across different technologies.
Parallel design flow
The use of a parallel design flow allows the designer to compress the FPGA prototype and ASIC development schedules. The illustration shown in Fig 2 reflects a design flow whereby the RTL is developed and targeted to the FPGA. In parallel, it is provided to the ASIC vendor for review and analysis. The ASIC vendor can make recommendations and modifications to the code for robustness. Timing scripts and clocking architectures are developed for both the FPGA and ASIC. Package selection for the ASIC is completed along with any SSO and power analysis. The PCB can be developed at this time to handle the large power hungry FPGAs with a path for migration to a smaller more efficient package for the ASIC.
2. A parallel FPGA and ASIC design flow.
The ASIC design can be placed on hold waiting for the final FPGA verifications to be complete, or until the product begins to ramp into production. More common is for the ASIC team to begin the logical design procedure once the design has become 80 to 90 percent stable. Including the development of the design for test (DFT) structures, initial floor planning, and cell placement, major changes to the design can be quickly run through the ASIC flow to ensure scripts for DFT and timing do not require modifications. The final timing convergence and physical design flow wait until the design is ready to move to the ASIC.
Design for portability
Decisions made during a product's FPGA design phase can significantly complicate the process of converting the product to a low cost ASIC for volume production. Therefore it is important to consider issues that will impact conversion during the FPGA design phase. This will allow the ASIC implementation to be done in a timely fashion with a minimum amount of effort. Some of these issues are as follows:
Plan for a potential voltage change (FPGA - ASIC): Design the system board to allow for a voltage change between the FPGA and ASIC implementation. FPGA devices are built in high-end technologies to allow for high performance and large gate counts. Often the same function and performance can be accomplished in an ASIC using an older technology node. This may require a higher core operating voltage. Design the printed circuit board (PCB) with an isolated power supply for the FPGA core. This will allow a simple regulator or resistor change to switch to a higher core voltage for the ASIC. A cost savings can be obtained by enabling the use of a less expensive technology node.
Plan for an ASIC JTAG implementation: Another board level issue to consider is the JTAG implementation. Often times an FPGA design does not use all of the available I/O for functional requirements, but all I/O are included in the board level JTAG implementation. If unused I/O must then be maintained in the ASIC implementation to match the original JTAG structure, the ASIC die size may increase and additional cost savings can be lost. It is best to employ a custom JTAG implementation for the ASIC using only the I/O required for the functional implementation.
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