Design Tools/Software
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Reusable VHDL IP in the real world
IP reuse is clearly a good thing. But in practice it has often proven surprisingly difficult to achieve. This article provides few principles and techniques that can be applied to make it more straightforward.
Partitioning an ASIC Design into Multiple FPGAs
This article outlines the most common approaches and flows to consider before you embark on your next partitioning project. Ultimately, you can accelerate the verification phase by using an ASIC prototyping approach that allows you to build multi-FPGA based prototypes of ASIC designs in an intuitive fashion, with little or no modifications to the original design.
Automating the FPGA design debug process
To elevate productivity, FPGA designers need to shift to the use of RTL for debugging their designs and not the gate-level description generated by synthesis.
EE Times' Top 10 Design Features of 2009
The top ten EETimes design features of 2009 show the conflicts inherent with grip of C on embedded programmers, the popularity of teardowns and the need for further education, both on the basics as well as cutting-edge design issues such as HDMI/DVI handshaking.
FPGA synthesis can be a leverage point in your design flow
Large FPGA devices pose significant challenges to an FPGA project team, requiring sound design flow practices. FPGA synthesis can provide significant leverage in achieving project cost, time and quality goals. This article discusses how FPGA synthesis tools can help designers achieve their goals efficiently and effectively.
FPGA-based rapid prototyping of ASIC, ASSP, and SoC designs
There are a variety of verification options available to engineers, each with its own advantages and disadvantages. In order to achieve high simulation speeds, it is necessary to use some form of hardware-assisted verification. This article discusses techniques and considerations for using FPGA-based prototypes, which provide very high speed with low cost.
FPGA design and verification in mechatronic applications
The VHDL-AMS language is an undiscovered asset for FPGA designers--a powerful tool to define and verify requirements in a non-digital context
Best of FPGA "lite" user guides
Over the past year and a half, Programmable Logic DesignLine has published several "lite" user guides detailing the use of products from Xilinx and Altera. These have proven very popular, so we've packaged them all together in one place, for your convenience.
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«March 2010 Design Tools/Software
About the Programmable Logic Design Tools/Software How-To Section
Programmable Logic DesignLine's Design Tool/Software Design Center section is the design resource for engineers looking to implement and use FPGA/CPLD tools and develop software for FPGA/CPLD architectures. Topics covered in this section include FPGA synthesis, EDA tools, formal and functional verification, DSP software design, DSP algorithm design, place-and-route design, and more.
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