Architecture/Implementation
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Dodging Amdahl's Law with message passing, FPGA-based, parallel processing
Most design teams agree that the basic plumbing of memory management can be the real bottleneck in heterogeneous processing. Today the only real solution is the microprocessor and co-processors sharing memory on the node, and then interconnecting many nodes with a GigE, Infiniband, or a custom interconnect configuring the nodes in a distributed memory layout.
Using SerDes in Fourth Generation Wireless Infrastructure
As the network equipment infrastructure is built up for 4G there will be an demand for high serial data rates between the main control radio equipment and that in distributed base stations. Here is how to meet the high serial data rate by only ugrading the Serdes through the use of a discrete solution
Using an FPGA to tame the power beast in consumer handheld MPUs
Shorter product lifecyles and lower volume consumer product families have led designers increasingly to turn to the FPGA for handheld-product development. But doing so requires grappling with new challenges in terms of area, speed and power.
Power Supply Design Considerations for Modern FPGAs
Today's FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently, power supply requirements may be more demanding, requiring special attention to features deemed less important in past generations. Failure to consider the output voltage, sequencing, power on, and soft-start requirements, can result in unreliable power up or potential damage to the FPGA.
10 most popular Programmable Logic DesignLine feature articles of 2009
As we prepare to turn the calendar to 2010, we've prepared a list of the 10 most popular design feature articles to appear on Programmable Logic DesignLine 2009.
Accelerating Bioinformatics Searching and Dot Plotting Using a Scalable FPGA Cluster
This paper presents an FPGA-based accelerated solution for DNA sequencing and dot plotting. It describes how multiple FPGA devices can be deployed to create a scalable cluster dedicated to the task of analyzing large amounts of data, and how this clustered hardware application can be connected to a software application for visualization and analysis.
High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems
Many video systems are implemented with feature-rich FPGA and multi-rate SDI integrated circuits that support high performance professional video transport over long distances. But FPGAs demand high density routing with fine trace width while high-speed analog SDI routing demands impedance matching and signal fidelity. This paper outlines the layout challenges facing hardware engineers and provides recommendations for dealing with these challenges.
I/O Design Flexibility with the FPGA Mezzanine Card
The FPGA's inherent flexibility has proven indispensable for the creation of external I/O interfaces. However, unless I/O is implemented on a daughter card (mezzanine module), replacing the physical I/O components and connectors requires changing the FPGA board design. The FPGA Mezzanine Card (FMC) standard, developed by a consortium of companies ranging from FPGA vendors to end users, specifically targets FPGAs, increasing I/O flexibility and lowering costs in a broad range of applications.
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«March 2010 Architecture/Implementation
About the Programmable Logic Architecture/Implementation How-To Section
Programmable Logic DesignLine's Architecture/Implementation section provides electronics engineers with insights into leading FPGA/PLD architectures, such as Virtex, Stratix, and more. At the same time, the FPGA/CPLD architecture section delivers insights into the implementation of these architectures in wireless, automotive, industrial, video, Digital TV, and other consumer electronics designs.
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