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ASIC designs continue to increase in size, complexity, and cost (for the purpose of these discussions, the term ASIC is assumed to encompass ASSP and SoC devices). At the same time, aggressive competition makes today's electronics markets extremely sensitive to time-to-market pressures. Furthermore, market windows are continually narrowing; in the case of consumer markets, for example, a "typical" ASIC design cycle is in the order of 9 to 18 months, while the window of opportunity for the introduction of a product using this device can be as little as 2 to 4 months.
Failing to have a product available at the beginning of the intended market window may result in significantly reduced revenue (or a complete loss of revenue and investment if the window is missed in its entirety). These factors have dramatically increased the pressure for ASIC designs to be "right-first-time" with no re-spins. In turn, this has driven the demand for fast, efficient, and cost-effective verification at both the chip and system levels.
Alternative Verification Technologies
There are a variety of verification options available to engineers, including software simulation, hardware simulation acceleration, hardware emulation, and FPGA-based prototypes. Each approach has its advantages and disadvantages.
Software simulators have the advantages of being relatively inexpensive and of providing very high visibility into the design. The disadvantage is that they are very slow with regard to simulating a large ASIC design. Even when running on a high-end workstation, it is possible to achieve equivalent simulation speeds of only a few Hz (that is, a few cycles of the main system clock for each second in real time). Thus, the software simulation of a large ASIC could take days, weeks, or (potentially) months. Practically, this means that detailed software simulations can be performed on only small portions of the design. Also, this makes software development and hardware-software co-verification impossible to do on a simulator. However, if a "window of interest" (a problem occurring around a specific time) can be identified by some other means, the software simulator can be used to perform a detailed analysis of the entire design around this temporal window.
In order to achieve high simulation speeds, it is necessary to use some form of hardware-assisted verification (HAV), of which there are three distinct categories as follows:
Acceleration: Hardware-based acceleration solutions typically involve arrays of special-purpose processor chips or FPGAs. A key consideration with regard to this form of acceleration is that it is simply geared to speeding the simulation of the ASIC in isolation; that is, this form of verification does not verify the device in the context of the system. Another concern is that such an accelerator can be very expensive; and this problem is exacerbated by the fact that each unit can be accessed by only one (or very few) developers at a time. Furthermore, the achievable acceleration is a function of the ratio between test bench activity and DUT (design under test) activity and typically provides an increase of only 2x to 10x over software simulation.
Emulation: Hardware-based emulation solutions also typically involve arrays of special-purpose processor chips or FPGAs. The advantage of emulation (as compared to acceleration) is that these representations are integrated into the system-level environment. The disadvantage is that they can achieve simulation speeds in the order of only 1 MHz, which is at least three orders of magnitude slower than the actual ASIC hardware, and which is simply not sufficient for many verification environments. And, once again, these units can be very expensive (millions of dollars per seat) and can be accessed by only one (or very few) developers at a time.
FPGA-based Prototypes: In many cases, it is necessary to verify the design "at-speed." In the case of a video processing chip, for example, part of the verification may involve evaluating the subjective quality of the video output stream. The solution is to create a hardware prototype of the ASIC design using one or more FPGAs. One important benefit of this approach is the ability to run external interfaces at full speed. As a functionally equivalent version of the ASIC, FPGA-based prototypes enable both chip and system-level testing. In addition to providing real-time simulation speeds in the order of 10 MHz to 100 MHz, such prototypes are relatively inexpensive, thereby allowing them to be provided to multiple developers and also to be deployed to multiple development sites. Due to their superior performance and affordability, FPGA-based rapid prototypes are ideal as pre-silicon software development platforms. The main problem with conventional FPGA-based prototypes is lack of visibility into the design; this issue is addressed by the Confirma platform, which is discussed later in this paper.
For the purposes of these discussions, we will concentrate on FPGA-based prototypes, which provide very high speed with low cost.
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