See also:
– Part 1 (Architecture)
– Part 2 (Programming Model)
– Part 3 (Student Project #1 – FIR Filter)
– Part 5 (Student Project #3 – Image Processor)
Editor's Note: ASICs, FPGAs, CPUs/DSPs, and SoCs have been joined by a new kid on the block – the Elemental Computing Array (ECA) from Element CXI. In Part 1 of this mini-series we introduced the ECA Architecture; in Part 2 we considered the programming model for these devices.
At that time we said that we would be presenting a number of real-world ECA-based projects, which have been implemented by students of Dr. Peter Athanas of the Department of Electrical and Computer Engineering at Virginia Tech in his Masters/PhD class on Configurable Computing. The interesting thing is that – within a couple of weeks of receiving the ECA design software and development boards – and with minimal training – these students managed to get a variety of projects up-and-running.
Thus, in Part 3, we presented a simple ECA-based FIR Filter design implemented by Abhranil Maiti. Now, in Part 4, we offer an ECA-based ZigBee Receiver design by Chen Zhang.
Introduction and motivation
The Elemental Computing Array (ECA) architecture and tools from Element CXI provide a unique electronic ecosystem enabling software-defined hardware. Features such as low power, flexibility, and fast real-time reconfiguration make the ECA a great platform for Software-Defined-Radio (SDR) systems. This article outlines the process of creating a commodity radio within the ECA architecture.
A software-defined radio provides communication devices with the ability to change the transmitted and received waveform without physically modifying the hardware circuits. Typical implementation platforms of SDR systems are general-purpose processors (GPPs), digital signal processors (DSPs) and field-programmable gate arrays (FPGAs).
Comparing to FPGAs, GPPs and DSPs, the ECA has higher computation density, lower power consumption, and higher structural robustness. As a Virginia Tech graduate student taking the Configurable Computing class, I have been interested in implementing a software-defined radio system on the ECA chip since it is a challenge that no one has tried before.
As part of my investigation, I chose to implement a ZigBee system. ZigBee is a low data rate, low-power, low-cost, wireless networking protocol based on the IEEE 802.15.4 standard for wireless personal area networks. Since this technology is simpler and cheaper than other wireless personal area networks, such as IEEE802.15.1/Bluetooth, ZigBee is becoming the standard approach for wireless sensors and embedded applications on the industrial, scientific, and medical radio bands.
The design process
A: Design tools
In this project, the following tools were used to implement the ZigBee receiver on the ECA device:
- Conceptual paper drawings of the overall design.
- CoWare's SPW, which provides a high-level design environment for a quick-start design via a drag-and-drop GUI interface.
- Element CXI's Alchemy/Crystal tools, which provides a design and simulation environment for converting a CoWare design into its corresponding Alchemy module and for performing low-level simulation.
B: Some issues and tips
Several issues have to be addressed and taken care of during the design and implementation. Some pertinent items are as follows:
- Since the ECA is a data-flow machine, the design method is totally different from the contemporary FPGA designs and DSP designs that I was used to.
- All of the operations of elements in an ECA are token-based. A token accompanies a valid input data point. Before an operation can be executed, all of the inputs must have valid input data. Token-based computation frees the designer from traditional synchronization issues, yet every token has to be taken care of.
- If two or more inputs go through different data paths and merge together finally, it is better to let all of the data paths have the same delay so that the system can work fast and smoothly in a pipeline mode. Otherwise, the latest-arrived input data may hold up all others at the merging end and slow down the whole system.
C: The overall design
A block diagram of the overall ZigBee design is shown in Fig 1. A ZigBee system uses an offset-QPSK modulation scheme that requires two channels to transmit signals; hence, the implemented receiver has two channel inputs. Since each of the four data bits of a QPSK symbol is mapped to a sequence of 32 'chips' and transmitted in the two channels at the transmitter-end, the first stage of the receiver is responsible for recovering the two chip streams from the two input signals. This is accomplished by two modules referred to as chip-recovers.
1. Block diagram for the overall ZigBee design.
(Click this image to view a larger, more detailed version)
The two chip-recovers are controlled by a chip synchronizer for aligning the chips and a received-signal-strength-indicator (RSSI) for detecting the presence of a valid input signal. Once the two chip streams are recovered, an I-Q channel detector determines the Q-channel chip stream in the two chip streams and locates the bit stream head.
In order to simplify this particular receiver implementation, the I-channel chip data is dumped and only the Q-channel chip data is used to extract the bit data by a bit-recover module since the I-channel transmits redundant data from the Q-channel.
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