Architecture/Implementation
Choosing a microcontroller and other design decisions - Part 2
This three-part article is abstracted from the book "Embedded Hardware Know It All", which provides a "360 degree" view from best-selling authors.
Choosing a microcontroller and other design decisions - Part 1
This three-part article is abstracted from the book "Embedded Hardware Know It All", which provides a "360 degree" view from best-selling authors.
Reconfigurable Computing: Custom Supercomputers on Demand?
RC creates an unprecedented opportunity for orders of magnitude improvement in GFlops-per-dollar, GFlops-per-watt, and just GFlops.
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Interconnect Design
Evolving passive optical networks (PONs) demand FPGA design flexibility
Standards uncertainties abound going forward with PONs; the bedrock for bridging those issues is scalability and flexibility, both of which are provided by FPGAs.
Comparing IP integration approaches for FPGA implementation
Avoiding the fixed routing and timetable of a standard bus can open up new avenues for design and restore a bit of glamour and creativity to an otherwise mundane project.
Back to the future: Low-cost, low-bit-rate serial communications with Manchester Encoding - Part 2
As a follow up to Part 1 on the basics of Manchester Encoding, Robert Guastella provides a realistic example of how to implement the protocol in a real world low bit rate serial wired or wireless design using a PIC MCU.
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Embedded Processing/DSP
Multirate DSP, Part 2: Noninteger sampling factors
Part 2 - How to change the sampling rate by a non-integer factor; Multistage decimation and polyphase filters; Upsampling and downsampling examples.
DSP Tricks: Reducing A/D Converter Quantization Noise
Ways to use oversampling and dithering to reduce analog to digital conversion quantization noise - DSP design hints and tricks that designers can use to make their algorithms more efficient.
Multirate DSP, part 1: Upsampling and downsampling
Part 1 introduces multirate signal processing, explaining how to upsample and downsample by an integer factor. MATLAB code included.
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FPGA-to-ASIC Conversion
FPGA-Based Prototyping - "Productivity to Burn"
This article highlights recent tool advances that can help you setup, implement, and verify your FPGA-based ASIC prototype faster than ever before.
Getting the most out of ASIC prototyping with FPGAs
This tutorial discusses various issues that must be taken into account when using an FPGA to prototype an ASIC or SoC design.
Hi def video scaler ASIC development from FPGA
How a high-definition video scaler ASIC implemented in a 0.18um standard cell technology was developed rapidly by starting with FPGA.
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Design Tools/Software
How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 1
Using advanced HDLs like SystemVerilog, current hardware modeling styles can be enhanced both in terms of abstraction levels and overall efficiency.
Binding the "Ties that Break" - Getting FPGA and PCB designers to meet at the I/O pin negotiating table
Getting the pin assignment portion of the design process under control is essential in order to realize any of the overall tangible benefits offered with FPGA's.
How to implement a high-definition video design framework for FPGAs
This article explores a video design framework that can allow for a faster design cycle; components can be used collectively or you can pick-and-choose as required.
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PROGRAMMABLE LOGIC DESIGN CENTER ARCHIVE
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About the Programmable Logic DesignLine How-To Section
Programmable Logic DesignLines' Design Center section delivers practical how-to information for the design and implementation of field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), gate arrays, and structured ASICs. Key topics covered in this section include: FPGA Tools/software, FPGA synthesis, DSP design, high-speed interconnects, FPGA/CPLD architectures, structured ASIC design, and embedded processing design.
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