Altera offers RapidIO 2.1 IP core

Altera's Serial RapidIO IP core supports up to four lanes at 5.0 GBaud per lane, addressing the increased bandwidth and reliability needs of the wireless and military markets, Altera (San Jose, Calif.) said. The core is optimized for Stratix IV FPGAs with embedded transceivers and is supported within Quartus II software v9.1, the company said.

The RapidIO 2.1 specification is designed to enable increased performance up to 20 GBaud in applications ranging from next-generation wireless basestations, high-performance military systems and DSP farms, Altera said. The Serial RapidIO IP core has been qualified against the RapidIO Trade Association's bus functional model and is supported within Altera's 40-nm Stratix IV GX and Stratix IV GT FPGAs and HardCopy IV GX ASICs, the company said.

The Serial RapidIO IP core, part of Altera's MegaCore IP library, is available now for evaluation upon download and installation of Quartus II software v9.1, Altera said. More information about Altera's Serial RapidIO solutions can be found on the company's website.

Related Links: Altera's RapidIO IP core passes Riolab device interoperability testing I/O Design Flexibility with the FPGA Mezzanine Card FPGA-based card provides high-speed I/O on AdvancedMC module

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