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SAN FRANCISCO—Pico Computing this week said it has achieved greater than 5000X acceleration of a bioinformatics sequence analysis and dot plot algorithm using a cluster of 112 commodity FPGA devices.
The FPGA computing platform consumes less than 300 Watts of power and fits into a standard 4U server case, according to Pico Computing (Seattle). The system uses 112 Xilinx Spartan-3 FPGAs, the company said.
A dot plot, also called a matrix plot, is a graphical tool for visualization enabling the comparison of two DNA sequences. A dot plot provides an easy way to understand a large amount of information about the relationship of two sequences, and serves as a framework for further analysis.
"The dot plot algorithm is an excellent example of how a scalable FPGA platform can speed the development and deployment of complex algorithms," Greg Edvenson, senior software engineer at Pico Computing and the developer of the accelerated bioinformatics application, said in a statement. "I was able to optimize and debug the core algorithm using a single, modestly-sized FPGA device, then scale to multiple FPGAs to achieve the desired levels of performance. This approach greatly reduced the overall development time."
The FPGA-accelerated dot plot algorithm, written in C-language, performs sequence analysis and pair-match scoring of DNA runs with lengths of 25 base pairs, Pico Computing said. The algorithm is inherently parallel, making it an ideal candidate for acceleration using large number of FPGA devices, according to the company.
Edvenson used a single FPGA device during initial algorithm development, according to Pico Computing. The FPGA was encapsulated in a Pico Computing E-17 card attached directly to a laptop computer via an ExpressCard interface, according to the company. After the algorithm was tested and working as a single hardware process, Edvenson then scaled up and replicated the algorithm for deployment on the FPGA cluster, the company said. C-to-FPGA tools provided by Impulse Accelerated Technologies were used during the development of the algorithms, reducing the need to write low-level HDL code, the company said.
"There are many advantages to using scalable clusters of lower-cost, power-efficient Spartan FPGAs for cluster computing," said Dr. Robert Trout, Pico Computing founder and CEO. "This approach reduces the overall cost per computation, and it also speeds development times because the FPGA placement and routing for each FPGA runs much faster than when working with larger, higher-density FPGA devices."
Pico Computing said it plans to demonstrate the FPGA-accelerated bioinformatics algorithm at the International Conference for High Performance Computing 200, November 14"20 in Portland, Ore.
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