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This is big. It's bigger than big. It's humongously huge! Well, that's certainly true of Altera's newly announced Stratix IV FPGA family, the largest member of which comprises 2.5 billion transistors! Leapfrogging the 45nm technology node, these devices have been implemented at what is being called the 40nm "half node".
But wait, there's more, because the folks at Altera are also announcing HardCopy IV ASICs at the 40nm node along with version 8.0 if their Quartus II design tool suite.
The Stratix IV FPGAs and HardCopy IV ASICs, both with transceivers options, provide unprecedented densities and performance while maintaining low-power consumption. The Stratix IV family has up to 680K logic elements (LEs); this is twice the size of the largest member of their Stratix III family, which Altera say was previously the largest FPGAs on the market. They also support up to 22.4 megabits of internal RAM and up to 1,360 18×18 multipliers.
The HardCopy IV ASIC family offers equivalent densities as the Stratix IV devices and features up to 13.3 million gates. These new 40nm devices are intended to meet the diverse high-end application needs in a large number of markets such as wireless and wireline communications, military, broadcast and ASIC prototyping.
One little snippet of news that came my way while chatting with the folks at Altera is that these devices boast a core performance of 350 MHz with a core voltage of 0.9V. Hmmm, I thought, that doesn't sound as impressive as I'd expected, surely their main competitor (whose name shall remain ... well, nameless) boasts memory and DSP blocks running at 550 MHz. "Ahhh, well," said the guys at Altera, "If you want to play that game, you could say that our memory and DSP slices run at up to 600 MHz." It seems that the 350 MHz number they are quoting is for 100% sustained operation all the way across the fabric, which is pretty darned impressive, let me tell you!
Click Here to see a video of your's truly chatting to the guys at Altera.
With the increasing demand for services such as video over Internet, high-speed wireless data and digital TV, designers need to deliver solutions that provide higher data rates, higher interface bandwidths, and increased data processing all in a power-efficient manner. To address these design challenges, Altera is leveraging its innovations in transceivers, memory interfaces, low-power technology and FPGA core architecture to offer new capabilities with its 40nm devices.
Manufactured on TSMC's 40nm process, the Stratix IV FPGA family is comprised of two variants, an enhanced variant rich with memory and digital signal processing (DSP) resources (Stratix IV E FPGAs) and an enhanced variant with transceivers (Stratix IV GX FPGAs). Stratix IV GX FPGAs offer up to 48 transceivers operating at up to 8.5 Gbps, which provides designers with the industry's highest available bandwidth, more than twice the bandwidth of any other FPGA. Stratix IV GX FPGAs also feature hard intellectual property (IP) support for PCI Express (PCIe) Gen 1 and 2 and also supports a wide range of protocols including, Serial RapidIO, XAUI (including DDR XAUI), CPRI (including 6G CPRI), CEI 6G, Interlaken, and Ethernet.
To address the low-power demands of today's applications and markets, the Stratix IV family members feature Altera's patented Programmable Power Technology. This power-saving technology optimizes logic, DSP, and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design.
For the first time, Altera offers a transceiver-based ASIC option with the new HardCopy IV ASIC family. Using the Stratix FPGAs in design delivers the benefits of FPGA hardware and software co-design and co-verification –saving months in time to market– and the use of HardCopy ASICs delivers the benefits of ASICs in production.
Availability
Customers can start their Stratix IV designs using Altera's Quartus II design software v.8.0. Engineering samples of the first member of the Stratix IV device family will be available in the fourth quarter of 2008. Customer tapeouts for HardCopy IV ASICs will start in the third quarter of 2009. For more information about Stratix IV devices, visit www.altera.com/stratix4. For information on HardCopy IV ASIC devices, visit www.altera.com/hardcopy4.
Whitepapers
- Click Here for the white paper titled: Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers
- Click Here for the white paper titled: Leveraging the 40-nm Process Node to Deliver the World's Most Advanced Custom Logic Devices
- Click Here for the white paper titled: Stratix IV Power Management and Advantages
- Click Here for the white paper titled: Increasing Productivity With Quartus II Incremental Compilation
Related Stories
Click Here to see what Mark LaPedus from EE Times thinks about this hot-off-the-press announcement from Altera.
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