LONDON — Xilinx Inc. has the final part of its Virtex-5 family available for general sampling. The Vitex-5 FXT FPGAs have one or two embedded PowerPC 440 processor blocks, high-speed RocketIO GTX transceivers and dedicated XtremeDSP processing capabilities.
This fourth platform in the 65nm Virtex-5 family provides what Xilinx describes as the 'ultimate system integration platform' for applications including wired and wireless communications, audio/video broadcast equipment, military, aerospace, and industrial systems.
According to Per Holmberg, director of worldwide marketing and sales mobilization at Xilinx it started shipping samples of the FXT variant last November with over 1000 devices already having been shipped to over 150 early access customers.
At the time of the initial Virtex-5 launch in May 2006 Xilinx was predicting that the FXT would be ready in the fist half of 2007 but Holberg says that the company has to have a complete design environment with all the support tools including development kits and software available before making devices generally available. "The biggest challenges was not in using the processor core itself - the 440 has been around for a while and is well proven - but to integrate it with the rest of the FPGA and the fabric through the switch matrix and the embedded DMA and bus interfaces in the most optimal way. The other challenge is to integrate the very high performance transceivers alongside the digital FPGA fabric. It is really putting all the pieces of the solution together before we go live including the IP, the characterization and the tools before we open the floodgates."
Each PowerPC 440 processor has integrated 32kbyte instruction and 32kbyte data caches and delivers up to 1,100 DMIPS at 550 MHz. Tightly coupled to these PC440 blocks is an integrated 5 x 2 cross bar processor interconnect architecture that provides simultaneous access to I/O and memory. This innovative interconnect architecture includes dedicated master and slave processor local bus interfaces, four DMA ports with separate transmit and receive channels, and a dedicated memory bus interface enabling high-performance, low latency point-to-point connectivity.
The advanced processor local bus (PLB) architecture maximises data transfers between the processor, crossbar and soft IP logic with high-throughput 128-bit interfaces to help minimise system bottlenecks. The auxiliary processor control Unit (APU) provides added connectivity for dedicated co-processing engines or custom user defined instructions in applications such as video processing, 3D data processing and floating-point math.
The PowerPC440 block in Virtex-5 FXT is supported by industry standard operating systems including Wind River Systems, Green Hills, and other key embedded OS providers. Linux support is provided through MontaVista, Wind River Systems with others soon to be added.
To increase I/O bandwidth, the Virtex-5 FXT platform includes low-power RocketIO GTX transceivers capable of supporting data rates from 500 Mbps to 6.5Gbps. Customers can design applications supporting standards such as XAUI, Fibre Channel, SONET, Serial RapidIO, PCI Express 1.1 and 2.0, Interlaken, and others.
Consuming less than 200mW typical power per channel at 6.5Gbps, the GTX transceivers include 4-tap DFE receiver equalization in addition to linear equalization and transmit pre-emphasis to improve signal integrity at higher line rates. The transceiver blocks also include a multi-code physical coding sublayer to support both 64B/66B and 64B/67B encoding/decoding schemes saving thousands of logic cells for each channel.
