See also:
– Part 1 (Architecture)
– Part 2 (Programming Model)
– Part 4 (Student Project #2 – ZigBee Receiver)
– Part 5 (Student Project #3 – Image Processor)
Editor's Note: ASICs, FPGAs, CPUs/DSPs, and SoCs have been joined by a new kid on the block – the Elemental Computing Array (ECA) from Element CXI. In Part 1 of this mini-series we introduced the ECA Architecture; in Part 2 we considered the programming model for these devices. Now, in Part 3, we present a real-world ECA-based design project from a PhD student at Virginia Tech.
Over the course of the next few weeks, we will be presenting a number of such projects, which have been implemented by students of Dr. Peter Athanas of the Department of Electrical and Computer Engineering at Virginia Tech in his Masters/PhD class on Configurable Computing. The interesting thing is that – within a couple of weeks of receiving the ECA design software and development boards – and with minimal training – these students managed to get a variety of projects up-and-running.
The hardware design process requires a number of critical steps that sometimes make the process complex in nature. Efforts are being made continuously to make abstraction at higher levels so that designers can do their job in a more efficient manner. The Element CXI design flow is quite useful in this respect, and it has the capability to carry out a complete hardware design flow from a high level of design abstraction, ultimately leading to a circuit"level implementation.
In this article, a simple example Element CXI ECA64 implementation is presented to illustrate the design steps. The example will show how a basic FIR filter can be created using the Element CXI design environment. This example could have been designed using a programming language to be run on a general-purpose processor, but a general-purpose processor is not fast enough in terms of throughput. A hardware implementation will certainly give better performance. This example will also highlight the key capabilities of an Element CXI design.
A Finite Impulse Response (FIR) filter is common operation in signal processing. There are different types of architectures for an FIR filter. In this example, a simple parallel FIR filter of direct form Type 1 is implemented as illustrated in Fig 1.
1. A simple parallel FIR filter of direct form Type 1.
This structure implements the filter equation of summation of products as follows:
. . . where x is the input sample sequence, h0 through h3 are the filter weights, and y is the computed output. In this example N has a value of 4. The structure above uses four multipliers, three adders, and six registers or delay elements.
The coefficients are h0, h1, h2, and h3. In the case of this example, the values of these coefficients have been kept at 0.25, with the result that our FIR filter is acting as an averaging filter.
The overall Element CXI design flow is outlined as illustrated in Fig 2:
2. Elemental Computing Array (ECA) development model.
(Click this image to view a larger, more detailed version)
In the beginning, the filter is modeled using SPD (Signal Processing Designer) by CoWare. This is an application with a well thought out graphical user interface. It contains many functional blocks that are used to build a system. For this particular ECA-based design process, only Element CXI design libraries can be used to implement the design on the target ECA64 device. System simulation and analysis are performed within the CoWare SPD environment to ensure the functional correctness of the system. SPD provides powerful capabilities for stimulating and observing a model under development.
Once the simulation is complete, the design is converted into an XML file. This file contains the design structure and data-flow information. From this point onwards, the process takes place in the Element CXI Alchemy SDK. The XML file is translated to an "Elemental Language" (.EL) file used in the next step of the flow. This .EL file is compiled to create a LEAF (Logical Extensible Application Format), which is subsequently converted to binary .UUU file, which can be used for simulation as well as implementation on the chip.
Fig 3 shows the block diagram of our FIR filter in CoWare SPD (this is the implementation of the filter illustrated in Fig 1).
3. Block diagram of FIR filter in CoWare SPD.
(Click this image to view a larger, more detailed version)
As was previously noted, this filter uses four multipliers, six registers, and three adders. The input sample sequence is injected into the system through the input port (shown in the upper-left-hand corner of Fig 3); four samples are delayed by registers and are then multiplied by four filter coefficients.
Next, all of the products are summed using adders. All the functional blocks used in the above design are taken from the Element CXI library so that this design can be synthesized. The library elements are available in the library window (presented on the left-hand side of Fig 3) and are easily dragged and dropped into the design area.
In the above figure, the green rectangles have following names and functions:
zminus1 – register (modeled as delay element in the SPD library)
const_16 – filter coefficient
mult_16 – 16-bit multiplier
add_16 – adder
Fig 4 shows the system view of the filter within the SPD environment. The rectangle in the middle named FIR_parallel contains the design shown in Fig 3. The design has been provided with a source signal and a sink for the purposes of simulation. Additional details including a full test bench could also be captured in SPD. The FIR_parallel functional block can be saved in the user-defined library and can be used in other applications where an FIR filter is needed. User can set the source with different types of signals for simulation.
4. System view of the filter within the SPD environment.
(Click this image to view a larger, more detailed version)
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