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Editor's Note: See also the related Product Release Article.
As FPGAs push the envelope of performance, understanding how to design for maximum performance requires knowledge of the device architecture and design software. Today's FPGAs resemble a true System-on-a-Chip (SoC) with many more sophisticated features than the glue logic FPGAs of the past. To maximize system performance, designers need to use proper design techniques such as defining timing constraints and selecting options in synthesis and implementation that work best for their design. This article describes how to achieve faster timing in the fewest design iterations.
Understanding the architecture
When evaluating a new FPGA architecture, it is important to understand the hardware features and the tradeoffs that can be made in the architecture. Datasheets, user guides, and technical papers on the architectural features should be thoroughly reviewed before moving forward with a design.
The first thing to learn about any FPGA is what makes up the basic fabric of logic. For example, each of the configurable logic blocks (CLBs) in a Xilinx Virtex-5 FPGA contains two slices; and each slice contains four 6-input look-up tables (LUTs), four registers, and dedicated carry logic. For maximum utilization of each slice, it is important to take into consideration the width of the LUTs, the connectivity between the basic elements, and any shared resources.
Many FPGA architectures also contain hard IP blocks, such as embedded memory and blocks used for DSP functions. If a hard-IP block continuously shows up as the source or destination of your critical path, there are a couple of things that can be analyzed to improve the performance. First, check to see if the design is making the most of the block's features and that the synthesis tool is inferring the features you expected from your RTL code. Use the dedicated pipeline registers inside the blocks to reduce the setup and clock-to-out timing. Evaluate the tradeoff between using dedicated blocks versus implementing the same function in slices to allow for placement flexibility. This can especially be important when using a high percentage of hard-IP blocks.
The clocking resources that are utilized in a design can also affect a design's performance. For example, Xilinx Virtex-5 FPGAs have I/O, regional, and global clocking resources. These devices are divided into clock regions which at most, can contain 4 regional clocks and 10 global clocks. During design planning, it is important to analyze how many clock regions are going to be used as well as specific clocks within a clock region. Placing your I/Os so that their interface logic does not require all the clock resources in a clock region gives the implementation tools greater placement flexibility.
Define timing requirements
Synthesis and implementation tools are driven by the performance goals that a user specifies with timing constraints. It is important to constrain all internal clock domains, input and output (I/O) paths, multi-cycle paths, and false paths. Define realistic timing constraints in synthesis order to prevent excessive replication.
In your synthesis report, check for any replicated registers and ensure that timing constraints that might apply to the original register also cover the replicated registers for implementation. When writing timing constraints for implementation, group the maximum number of paths with the same timing requirement first before generating a specific timing constraint. By consolidating constraints, implementation runtime and memory usage can be minimized.
Example of non-consolidated constraints (Xilinx constraint syntax)
TIMESPEC "TS_firsttimespec" = FROM "flopa" TO "flopb" 10ns;
TIMESPEC "TS_secondtimespec" = FROM "flopc" TO "flopb" 10ns;
TIMESPEC "TS_thirdtimespec" = FROM "flopd" TO "flopb" 10ns;
Consolidation of constraints using grouping
INST "flopa" TNM = "flopgroup";
INST "flopc" TNM = "flopgroup";
INST "flopd" TNM = "flopgroup";
TIMESPEC "TS_consolidated" = FROM "flopgroup" TO "flopb" 10ns;
Driving synthesis
For a synthesis tool to create a high-performance circuit, the tool needs to be properly driven by the designer. The first thing a designer needs to consider is proper coding techniques to ensure that inference of behavioral RTL made by the synthesis tool leads to the maximum usage of the architectural features. For example, Xilinx ISE Project Navigator's language templates – available in both Verilog and VHDL – are a great place to get coding examples.
Next, make sure that the synthesis tool has a complete picture of the design. If a design contains IP netlists or any other lower level black-boxed netlists, these netlists should be included in the synthesis project. Although the synthesis tool won't optimize any logic within the netlist, it will have a better understanding of how to optimize the HDL that interfaces to these lower level netlists.
The tool also needs to understand the performance goals of a design using the timing constraints supplied by the designer. If there are critical paths in the implementation that are not seen as critical in synthesis, try Synplicity Synplify PRO's –route constraint to force synthesis to focus on that path. Finally, there are a variety of tool settings in synthesis that should be explored. Refer to Fig 1 for suggested tool settings for Synplify PRO.
1. Suggested tool settings for Synplify PRO.
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