SAN FRANCISCO — Electronic system level (ESL) EDA startup Calypto Design Systems Inc. Monday (May 22) released version 2.0 of its SLEC sequential logic equivalence checking product family, claiming a breathtaking 100x increase in capacity over previous releases of the tool.
According to Mitch Dale, Calypto's director of product marketing, SLEC’s 100x capacity increase for system-level design is achieved through a combination of improvements in Calypto's sequential analysis engine and formal solvers. In addition to the hybrid formal engine found in SLEC 1.0, Dale said, Calypto has developed a new patent-pending sequential analysis algorithm that essentially does "on-the-fly" optimization, eliminating vast amounts of redundant state information. With this increase, SLEC can handle System-Level design blocks such as fast Fourier transforms and discrete cosine transform algorithms, Dale said.
“Today’s SoC [system-on-chip] designers need to move to system-level design to drive innovation and enhance their competitive advantage,” said Tom Sandoval, Calypto CEO, in a statement. “SLEC 2.0 is the only technology that enables designers to bridge a system-level model to its equivalent RTL implementation, independent of sequential differences. It is the key technology that is enabling ESL.”
According to Calypto (Santa Clara, Calif.), the foundation of sequential analysis is the ability to deal with large, complex changes in design state and abstraction. Sequential changes are common when comparing functional system-level designs with cycle accurate RTL designs, Calypto said, adding that SLEC 2.0 can handle designs in which the state and temporal differences are measured in the millions.
Calypto rolled out version 1.0 of SLEC with much fanfare last April. The tool serves to verify that an RTL block is functionally equivalent to a higher-level block written in VHDL, Verilog, SystemC or C/C++ and also to verify that sequentially different versions of an RTL block are functionally equivalent. The product has garnered the attention of the industry for providing a fundamentally different approach. To date, Calypto has disclosed only two SLEC customers — Renesas Technology Corp. and Freescale Semiconductor Inc. — but the company has said that more customer adoption announcements, as well as announcements of more partnerships on ESL methodology, would be forthcoming.
Calypto plans to demonstrate version 2.0 of SLEC at the Design Automation Conference (DAC) here July 24-27. The SLEC 2.0 product family is immediately available with support for Verilog, VHDL, SystemC and C/C++ hardware descriptions, Calypto said. SLEC 2.0 runs on Linux operating systems and is priced from $175,000, the company said.
